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SP8531
SIGNAL PROCESSING EXCELLENCE
12-Bit Sampling Serial Out Analog to Digital Converter
s s s s s s s 12 Bit Resolution Single +5Volt Supply Internal Reference, 1.25V Unipolar 0 to +2.5 Volt Input Range Fast, 3.75 s Conversion Time Fast Power Shutdown/Turn-On Mode 3-Wire Synchronous Serial High Speed Interface s 2A Shutdown Mode (10W) s Low Power CMOS 60mW typical
DESCRIPTION The SP8531 is a sampling 12-Bit serial out analog to digital converter. The device contains a high speed 12-Bit analog to digital converter, internal reference, and sample/hold circuitry. The SP8531 is available in 16-pin PDIP and SOIC packages, specified over Commercial and Industrial temperature ranges.
CS
CONTROL LOGIC
STATUS COUNTER BUFFER
SCLK SAR
VIN CDAC OFFSET ADJUST SHUTDOWN RTRIM BUFFER REF. LATCHED COMPARATOR DOUT
GAIN ADJUST REF OUT
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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ABSOLUTE MAXIMUM RATINGS
(TA=+25C unless otherwise noted) .............................................. VDD to DGND ............................................................. -0.3V to +7V VDA to AGND .............................................................. -0.3V to +7V Vin to AGND .................................................... -0.3V to VDA +0.3V Digital Input to VSS ........................................... -0.3V to VDD+0.3V Digital Output to VSS ........................................ -0.3V to VDD+0.3V Operating Temp. Range Commercial (J,K Version) ............................... 0C to 70C Industrial (A,B Version) .............................. -40C to +85C Storage Temperature ............................................... -65C to 150C Lead Temperature(Solder 10 sec) ....................................... +300C Power Dissipation to +70C ................................................ 500mW Derate Above 70C ......................................................... 10mW/ C
SPECIFICATIONS
Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25C.
PARAMETER DC Accuracy Resolution Integral Linearity J, A K ,B Differential Linearity Error J, A K ,B Gain Error J, A K,B Offset Error J, A K,B Analog Input Input Impedance Conversion Speed Sample Time Conversion Time Complete Cycle Conversion Rate: Clock Speed
MIN.
TYP. 12 +0.6 +0.4 +0.5 +0.5 +0.2 +0.1 +4 +3 0 to 2.5 600K
MAX.
UNIT Bits
CONDITIONS
+1.0 +0.75 +1.0 +1.0 +1.0 +0.5 +7 +5
LSB LSB LSB LSB %FSR %FSR LSB LSB Volts Ohms ns s s No Missing Codes No Missing Codes
Externally Trimmable to Zero Externally Trimmable to Zero
Externally Trimmable to Zero Externally Trimmable to Zero
4 MHz Clock Rate
400 3.75 4.25 235 4
KHz MHz
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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SPECIFICATIONS (continued)
Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25C.
PARAMETER Reference Output Ref. Out Temp. Coef. J, A K,B Ref.Out Error Output Current Digital Inputs Input Low Voltage , VIL Input High Voltage , VIH Input Current IIN Input Capacitance Digital Outputs Data Format (1) Data Coding (2) VOH VOL AC Accuracy Spurious Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal to Noise & Distortion (SINAD)
MIN.
TYP. 1.25 30 20 +4 1
MAX.
UNIT Volts ppm/C ppm/C
CONDITIONS
+25
mV mA Volt Volt VDD= 5V +5% VDD= 5V +5%
0.8 2.0 +1 3
A pF
4.0 0.4
Volt Volt
VDD=5V5%, IOH=-0.4mA VDD=5V5%, IOL=+1.6mA fin=47KHz,VDD=5.0V @ 25C, SCLK=4MHz
83
dB
-80
dB
71
dB
Signal to Noise (SNR)
72
dB
Sampling Dynamics Acquisition Time to 0.01% -3dB Small Signal BW Aperture Delay Aperture Jitter 200 13 35 10 ns MHz ns ps RMS For a +FS step change at input
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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SPECIFICATIONS (continued)
Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25C.
PARAMETER Power Supplies VDD Supply Current Operating Mode Shutdown Mode Power Dissipation Operating Mode Shutdown Mode Power Turn On Temperature Range Commercial Industrial Storage
MIN.
TYP.
MAX.
UNIT
CONDITIONS
4.75 11.5 0.01 60 0.05
5.25 17 2 85 10 20
Volts mA A mW W S SD=0, VDD=+5.0V SD=1, VDD = +5.0V SD=0 SD=1 Via Shutdown Control to 1 LSB settling error.
0 -40 -65
to to to
+70 +85 +150
C C C
(1) Data Format is 12-Bit Serial (2) Data Coding is Binary (See Timing Diagram)
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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PIN ASSIGNMENTS Pin 1-N.C.-No Connection Pin 2-N.C.-No Connection Pin 3-VIN - Analog Input Pin 4-AGND-Analog Ground Pin 5-VSS-Digital Ground Pin 6-SCLK-Serial Clock Input Pin 7-DOUT Digital Data Output Pin 8-STATUS- High During Conversion Pin 9-CS-Chip Select Bar Input High Deselects chip -Low Selects chip Pin 10-SD-Shutdown Input, logic low=power up, logic high = powerdown Pin 11-VDD Digital +5V supply Pin 12-VDA Analog +5V supply Pin 13-OffADJ- External Offset Adjust Pin 14-N.C.-No Connection Pin 15-REFOUT-Voltage Reference Output Pin 16-GAINADJ-External Gain Adjustment
N.C. N.C. VIN AGND VSS SCLK DOUT STATUS 1 2 3 4 5 6 7 8 16 15 14 13 GAIN ADJUST REF OUT N.C. OFFSET ADJ. VDA VDD SD CS
CIRCUIT OPERATION Figure 1 shows a simple circuit required to operate the SP8531. The conversion is controlled by the user supplied signal Chip Select Bar (CS) which selects and deselects the device, and a system clock (SCLK). A high level applied to CS asynchronously clears the internal logic, puts the sample & hold (CDAC) into sample mode and places the DOUT (Data Output) pin in a high impedance state. Conversion is initiated by falling edge on CS in slave mode at which point the input voltage is held and a conversion is started. A delay of 90ns is required between the falling edge of CS and the first rising of SCLK. The device responds to the shut down signal asynchronously so that a conversion in progress will be interrupted and the resulting data will be erroneous. A 20 Sec minimum delay is required between the falling edge of shut down and initiation of a conversion. Data Format 16 bits of data are sent for each conversion. The data is shipped with 4 leading "0"s, and then 12 bits of data, MSB first. Data changes on the falling edge of SCLK and is stable on the rising edge of SCLK. Continuous stand alone operation is obtained by holding CS low. In this mode an oscillator is connected directly to the SCLK pin. The SCLK signal along with the STATUS output Signal are used to synchronize the host system with the converter's data. In this mode there is a single dead SCLK cycle between the 16th clock of one conversion and the first clock of the following conversion for the SP8531. At a clock frequency of 4 MHz the SP8531 provides a throughput rate of 235KHz. In slave mode operation, CS is brought high between each conversion so that all conversions are initiated by falling edge on CS.
SP8531
12 11 10 9
FEATURES The SP8531 is a sampling, 12-Bit serial out data acquisition system. The device contains a high speed 12-bit analog to digital converter, internal reference, and sample and hold circuitry. The SP8531 is fabricated in Sipex' Bipolar Enhanced CMOS Process that permits state-ofthe-art design using bipolar devices in the analog/linear section and extremely low power CMOS in the digital/logic section.
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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10kOhms 1 2 VIN 3 4 5 6 7 CLOCK IN DATA OUT STATUS OUT CHIP SELECT SHUTDOWN * Optional filter capacitor is helpful in a noisy pc board application. 8 N.C. N.C. VIN AGND VSS SCLK DOUT STATUS GAIN ADJUST 16 REF OUT 15 N.C. 14 OFFSET ADJ. 13 VDA 12 VDD 11 SD 10 CS 9 6.8F 0.1F +5V 0.1F + 6.8F 2kOhms 5kOhms
SP8531
Figure 1. Operating Circuit
Input Impedance The input of the SP8531 can be modeled as a resistor in series with a ground referenced DC voltage source of 1.0 volt. Note that the input resistor is a switched capacitor resistor and so its value is inversely proportional to conversion rate. When the ADC is in free running mode with a 4 MHz clock applied (a conversion rate of 235 Ksps) the input resistance is nominally 600K. At a conversion rate of 117.5 Ksps the input resistor value would double to 1.2 megohms. In order to avoid introducing an unadjusted gain error greater than 1 lsb, the device must be driven by a source whose resistance is 4096 times smaller than its input impedance. At the 4 MHz clock rate this would require a source whose resistance was less than 146 Ohms. Layout Considerations Because of the high resolution and linearity of the SP8531, system design considerations such as ground path impedance and contact resistance become very important. To avoid introducing distortion when driving the analog inputs of these devices, the source resistance must be very low, or constant with signal level. Note that in the operating circuit there is no connection made between VDA (Pin 12) and the system power supply. This is because the analog supply pin (VDA) is connected internally to the digital supply pin (VDD) through a ten ohm resistor. This ten ohm resistor when combined with a parallel combination of 6.8F tantalum and 0.1F ceramic capacitor between VDA and analog ground, will provide some immunity to noise which resides on the system supply. To maintain maximum system accuracy, the supply connected to the VDD pin should be well isolated from digital supplies and wide load variations. To limit effects of digital switching elsewhere in a system, it often makes sense to run a separate +5V supply conductor from the supply
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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regulator to any analog components requiring +5V including the SP8531. Noise on the power supply lines can degrade the converters performance, especially corrupting are noise and spikes from a switching power supply. The ground pins (AGND and VSS) on the SP8531 are separated internally and should be connected to each other under the converter. Applying the technique of using separate analog and digital ground planes is usually the best way to preserve dynamic performance and reduce noise coupling into sensitive converter circuits. Where any compromise must be made the common return of the analog input signal should be referenced to the AGND pin of the converter. This prevents any voltage drops that might occur in the power supply's common return from appearing in series with the input signal. Coupling between analog and digital lines should be minimized by careful layout. For instance, if analog and digital lines must cross they should do so at right angles. Parallel analog and digital lines should be separated from each other by a trace connected to common. If external gain and offset potentiometers are used, the potentiometers and related resistors should be located as close to the SP8531 as possible.
Minimizing "Glitches" Coupling of external transients into an analog to digital converter can cause errors which are difficult to debug. In addition to the above discussions on layout considerations, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance from a system using the SP8531 converter. These potential system problem sources are particularly important to consider when developing a new system, and looking for causes of errors in breadboards. First, care should be taken to avoid transients during critical times in the sampling and conversion process. Since the SP8531 has a internal sample/hold function, the signal that puts the device into hold state (CS going low) is critical, as it would be on any sample/hold amplifier. The CS falling edge should have a 5 to 10 ns transition time, low jitter, and have minimal ringing, especially during the first 20ns after it falls.
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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TIMING CHARACTERISTICS
(Typical @ 25C with VDD = +5V, unless otherwise noted)
PARAMETER Thoughput Time (tTP=tA+tC) Acquisition Time (tA) (2 SCLK Periods) Conversion Time (tC) (15 SCLK Periods) SCLK Low Pulse Width (tSKL) SCLK High Pulse Width (tSKH) SCLK Period (tSKT) Bus Access Time (tCBA) Bus Relinquish Time (tBR) Setup Time -SCLK Falling to CSN Falling (tCSSU) CSN Low Before SCLK Rises (tCS) SCLK Falling to Data Valid (tSD) CSN Falling to status Rising (tDCS) SCLK 17 Falling to Status Rising Free Run (tDSS) SCLK 16 Falling to Status Falling ( tDSE) Delay SD Low to initiate Conversion (tPU) Aperture Delay Slave-Mode (tAPC) Aperture Delay Free-Running Mode (tAPS)
MIN. 4.25 400 3.75 110 110 250
TYP.
MAX.
UNIT s
COND.
500
ns s
125 125
ns ns ns
51 45 0 90 50 69 70 45 5 30 35
ns ns ns ns ns ns ns ns s ns ns
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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SP8531DS/01
TIMING DIAGRAMS
Slave Mode
1 2 3 4 5 6 15 16 1 2 3 4 5 6 15 16 DATA WORD N D11 D10 D0 DATA WORD (N+1) D11 D10 D0 HI-Z
SCLK
CSN
STATUS
DOUT
HI-Z
tCSSU tCS tSKH 1 2 4 tSKT 3 tAPC tDCS tPU tCBA
tSKL tSD 5 15 16
tDSE
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
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tC
SCLK
tBR
CS
STATUS D11 D10 CONVERT D1 D0 tA AQUIRE
DOUT
MODE
AQUIRE
(c) Copyright 1999 Sipex Corporation
SD
SP8531DS/01
TIMING DIAGRAMS
Free Running Mode
17 1 2 3 4 5 6 15 16 17 1 2 3 4 5 6 15 16 17 1 2 DATA WORD (N+1) D0 D11 D10 D1 D0 DATA WORD N D1 D11 D10
15
16
SCLK
CSN
STATUS
DOUT D1
D0
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
10
tDSS tSKT tSD 4 5 6 2 3 tSKH 1 tSKL "0" D11 tC CONVERT D10
tAPS
tSDE 15 16 17 1
SCLK 17
CSN
STATUS D1 D0 tA AQUIRE "0" CONVERT
DOUT
(c) Copyright 1999 Sipex Corporation
MODE AQUIRE
Communication to DSP TMS320C26 in Free-Run To use free-run mode the chip select on the SP8531 must be low and is therefore tied to ground. Since status gives a low pulse before the start of conversion, this signal is used to provide the necessary Frame Sync Receive (FSR) pulse to start reading the data. All it needs is an inverter to provide for the correct logic level.
The Data Out (Dout) can be connected directly to the Data Receive (DR) of the DSP and both elements use the same externally provided clock. The minimal hold time for DR after falling edge of CLKR is 20ns where the typical hold time for the SP8531 is 50ns making the data read valid. Note that although the SP8531 is essentially a 12 bit converter, it sends 16 bits with the four MSB's as zero's.
VIN
VIN
STATUS CS
FSR
SP8531
DOUT
DSP TMS320C26
DR
SCLK CLK
CLKR
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
SP8531DS/01
CLKR=SCKL:
STATUS:
FSR:
0 0 0 0 D8 D7 D6 D5 D4 A1 A1 MSB A2 A4 A7 A8 A5 A6 A3 A9 A10 A11 A12 A13 A14 A15 A16 LSB B1 D11 D10 D9 D3 D2 D1 D0
DOUT:
DR:
RINT: TIMING DIAGRAM FOR SP8531 TO DSP TMS320C26
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
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CLKR, SCLK:
DOUT: DR:
tR
tR = 50 ns typ. tR min = 20 ns
(c) Copyright 1999 Sipex Corporation
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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PACKAGE: PLASTIC DUAL-IN-LINE (NARROW)
E1 E
D1 = 0.005" min. (0.127 min.) D
A1 = 0.015" min. (0.381min.) A = 0.210" max. (5.334 max). A2 C O eA = 0.300 BSC (7.620 BSC) L
e = 0.100 BSC (2.540 BSC)
B1 B
ALTERNATE END PINS (BOTH ENDS)
DIMENSIONS (Inches) Minimum/Maximum (mm) A2 B B1 C D E E1 L O
8-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
14-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
16-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
18-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
20-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
22-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
0.355/0.400 0.735/0.775 0.780/0.800 0.880/0.920 0.980/1.060 1.145/1.155 (9.017/10.160) (18.669/19.685) (19.812/20.320) (22.352/23.368) (24.892/26.924) (29.083/29.337) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15)
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
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PACKAGE: PLASTIC SMALL OUTLINE (SOIC)
E
H
D A O e B A1 L
DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H L O
14-PIN 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.348/0.363 (8.83/9.22) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
16-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.398/0.413 (10.10/10.49) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
18-PIN 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.447/0.463 (11.35/11.74) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
20-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.496/0.512 (12.60/13.00) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC)) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
24-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.599/0.614 (15.20/15.59) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
28-PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.697/0.713 (17.70/18.09) 0.291/0.299 (7.402/7.600) 0.050 BSC (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
SP8531DS/01
SP8531 12-Bit Sampling Serial Out Analog to Digital Converter
(c) Copyright 1999 Sipex Corporation
15
ORDERING INFORMATION
Model segment Model ..................................................... INL Linearity (LSB) ............................. Temperature Range .................................... Package Types SP8531JN ........................................................... 1.0 ................................................ 0C to +70C ............................... 16-pin, 0.3" Plastic DIP SP8531JS ........................................................... 1.0 ................................................ 0C to +70C ........................................ 16-pin, 0.3" SOIC SP8531KN ......................................................... 0.75 ............................................... 0C to +70C ............................... 16-pin, 0.3" Plastic DIP SP8531KS ......................................................... 0.75 ............................................... 0C to +70C ........................................ 16-pin, 0.3" SOIC SP8531AN .......................................................... 1.0 ............................................... -40C to +85C ............................. 16-pin, 0.3" Plastic DIP SP8531AS .......................................................... 1.0 ............................................... -40C to +85C ...................................... 16-pin, 0.3" SOIC SP8531BN ......................................................... 0.75 .............................................. -40C to +85C ............................. 16-pin, 0.3" Plastic DIP SP8531BS ......................................................... 0.75 .............................................. -40C to +85C ...................................... 16-pin, 0.3" SOIC Please consult the factory for pricing and availability on a Tape-On-Reel option.
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (978) 934-7500 FAX: (978) 935-7600 European Sales Offices: ENGLAND: Sipex Corporation 2 Linden House Turk Street Alton Hampshire GU34 IAN England TEL: 44-1420-549527 FAX: 44-1420-542700 e-mail: mikeb@sipex.co.uk Far East: JAPAN: Nippon Sipex Corporation Yahagi No. 2 Building 3-5-3 Uchikanda, Chiyoda-ku Tokyo 101 TEL: 81.3.3256.0577 FAX: 81.3.3256.0621
GERMANY: Sipex GmbH Gautinger Strasse 10 82319 Starnberg TEL: 49.81.51.89810 FAX: 49.81.51.29598 e-mail: sipex-starnberg@t-online.de
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. SP8531DS/01 SP8531 12-Bit Sampling Serial Out Analog to Digital Converter (c) Copyright 1999 Sipex Corporation
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